The present invention relates to a fast calculation method and, more particularly, to a fast calculation method and its hardware apparatus using a linear interpolation operation to reduce the complexity of the hardware and increase the speed of the calculation.
The ways for processing signals in devices such as computers, processors and the like are divided into two categories, one is an analog signal processing for continuous signals and the other one is a digital signal processing for discrete signals. The digital signal processing is selected more frequently than the analog signal processing since the digital signal processing can directly perform a complicated mathematical operation on signal values, greatly increasing the operative flexibility thereof. A digital signal is a combination of discrete sampling values obtained from sampling an analog signal in a fixed sampling frequency. Therefore, digital signals will become more analytical by picking a value between two sampling values through an interpolation operation.
The interpolation operation can be either simple or complicated, depending on which kind of the interpolation operation has been taken. The simplest one is a zero-order interpolation operation which regards a target point, that is, an interpolation value, as the first one of the two sampling points. Although the zero-order interpolation operation is very simple because what the zero-order interpolation operation needs to do is merely duplicate the first sampling point of the two rather than performing any computation, a lot of quantized noise signals will be introduced and thus, the quality of the interpolation operation is poor. A more useful interpolation operation is a linear interpolation operation which considers the relation between two sampling points to be linear and the target point will be obtained through a proportional computation. The linear interpolation operation becomes the most commonly chosen method because the computation amount of the linear interpolation operation is not too much but the effect in reducing the quantized noise signals is remarkable.
To raise the analytic degree of a signal and to reduce the quantized noise signal, adding a linear interpolation function into a circuit will without doubt increase the complexity of the circuit. For example, obtaining a target point I between a point X and a point Y, as shown in FIG. 1, the operations including an addition, a subtraction, multiplications and a division have to be taken in the following expression. EQU I={(16-K)*X!+(K*Y)}/16
When the expression described above is implemented by a hardware, the following two problems will be faced.
(1) In the event that a signal X and a signal Y are quantized and encoded to data with 8 bits, expressions of (16-K)*X! and (K*Y) can be operated through a multiplier with a dimension of 8 bits by 4 bits. But operations in such a way will increase the complexity of the circuit and the manufacturing cost by a wide margin. Moreover, a modified design will be required by changing the multiplier with a dimension of 8 bits by 4 bits to a multiplier with a dimension of 8 bits by 5 bits or 8 bits by 6 bits if linear interpolation operations of dividing into 32 equal parts, 64 equal parts, and so on are further to be taken.
(2) In the event of merely substituting an adder for a multiplier, the expressions of (16-K)* X! and (K*Y) will require to repeat an accumulative addition operation 16 times in total to complete the entire operation. Operations in such a way are considerably time consuming and a counter has to be externally added to control the time the accumulative addition operates. Additionally, the times of repeating the accumulative addition operation have to be raised higher than 32 times, 64 times, and so on if linear interpolation operation of dividing into 32 equal parts, 64 equal parts, and so on are further to be taken.